Semiconductor memory device

ABSTRACT

A semiconductor memory device enabling efficient repair of defects by using limited redundant memory while suppressing a drop of access speed accompanied with the repair of defects of the memory, wherein a first memory array is divided into a plurality of memory regions for each 16 word lines and wherein defective memory addresses in regions are stored in a second memory array. When a memory address for accessing the first memory array is input, the defective memory address of the memory region including the memory to be accessed is read out from the second memory array. In this way, the addresses of defective memory in 16 word lines worth of a memory region are stored in the second memory array  2 , therefore addresses of a wider range of defective memory can be stored. For this reason, it becomes possible to repair defects occurring at random efficiently.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor memory device havingthe function of switching access to defective memory in a memory arrayto access to redundant memory provided in advance.

2. Description of the Related Art

In recent years, advances in semiconductor miniaturization technologyhave led to remarkable advances in the increase of capacity ofsemiconductor memories. On the other hand, however, a signal generatedfrom a miniature memory cell becomes very weak, so the statisticalprobability of occurrence of cell defects accompanied with variations inthe production process becomes high.

Defects of memory cells are generally dealt with by referring to adefect map describing addresses etc. of the defective cells for eachrepair unit. Conventionally, the defect map is programmed in fuses etc.provided inside the semiconductor memory. Defective cells and redundantcells are exchanged based on this defect map. Defective cells andredundant cells are frequently exchanged for entire large groups such asword line units and bit line units. However, many statistical celldefects explained above occur at random in small units. Therefore, toomany fuses and redundant cells must be prepared with the method of usinglarge repair units and not all of the defects can be repaired.

In order to deal with such a problem, the technique has been proposed ofusing a defect map stored in a nonvolatile memory etc. provided in thechip so as to reduce the repair units to the units of bits, bytes, andwords.

For example, there is the technique of individually providing a datacell array, a redundant cell array, and a defect address memory portion.The defect address memory portion stores addresses of rows and columnsfor specifying defective cells in the data cell array. When one of theplurality of defect addresses stored in the defect address memoryportion coincides with the input address, the redundant cellcorresponding to the coinciding defect address is selected and accessedin place of the defective cell. Due to this, the defective cells in thedata cell array are replaced by memory cells in the redundant cell arrayin units of bits.

However, when preparing a defect map common to the entire memory area inthis way and trying to repair random defects based on this, it isnecessary to scan all addresses stored in the defect address memoryportion and repair the cells of the addresses coinciding with the inputaddresses. This does not become a major problem when there are fewdefects, but when a large amount of defects occur, it becomes necessaryto mount a comparison circuit for each of the large number of defectaddresses, so an enormous number of comparison circuits becomenecessary. Accordingly, this technique is not preferred both from theviewpoints of the occupied circuit area and the comparison and searchtime.

Contrary to this, the technique has also been proposed of dividing thememory area in accordance with the addresses and providing a defect mapfor repairing random defects for each divided section. Each defect mapincludes information for specifying the defective cells limited to thecorresponding section. The defect map corresponding to the section ofaccess target can be selected by decoding an input address. According tothis technique, each defect map can be reduced in scale, so a reductionof the comparison circuit and a shortening of the delay time can beachieved.

For example, there is a technique of converting the input addresses toindex parts and tag parts and dividing the memory area by using theindex parts. According to this technique, there is provided a defectrepair memory separately from the main memory. The defect repair memorystores the defect maps and provides redundancy memory cells. When anaddress is input to the memory device, the input address is converted toan index part and tag part, then the defect map corresponding to theindex part is selected by decoding the index part and the selecteddefect map is read out from the defect repair memory. Then, thedefective memory cell is specified by referring to the read defect mapand the tag part.

Japanese Unexamined Patent Publication (Kokai) No. 11-120788 proposes aconfiguration providing redundant cells and the defect map storage cellsas sets on the same rows in the memory array in addition to the datacells. In Japanese Unexamined Patent Publication (Kokai) No. 11-120788,one row in the memory array can be regarded as a memory regioncorresponding to the section or index part. When a row of the memory isselected according to a row address of the input address, the defect mapcorresponding to that row is simultaneously selected, and the defectlocation in the row is specified. By this, it becomes possible to repairrandom defects for each row.

Summarizing the problems to be solved by the invention, the repairingmethod of defective memory cells explained above is effective as a basicconcept, but when applying it to an actual memory chip, there are thefollowing disadvantages.

For example, in the technique of converting input addresses to indexparts and tag parts, the conversion is only “performed so as to optimizethe repair efficiency”. Namely, index parts can be physically linkedwith word line selection addresses of the defect repair memory, but thephysical link between the defect repair memory and the main memoryremains in an arbitrary state.

As a result, an access operation to the main memory and the defectrepair memory are not related to each other and synchronized, butcompletely independently. Accordingly, whenever an address for accessingthe main memory is input from the outside, the input address must beconverted to an index part and a tag part, the word line of the defectrepair memory corresponding to the index part must be selected, and thedata must be read out from the defect repair memory by activating asense amp circuit thereof.

On the other hand, when the main memory is for example a DRAM, therandom access is carried out at a relatively low speed, but the randomaccess and burst access of the CAS (column address strobe) performedafter activating a word line are carried out at an extremely high speed.Further, the same high speed access is possible also in a relatively lowspeed flash memory etc. In general, the technique of selecting the rowaddress and outputting data groups read out from the memory cells on thesame word line to a latch circuit in parallel, then accessing the datagroups of the latch circuit at a high speed according to the columnaddress is used in various memories.

Accordingly, when using such a high-speed access mode, the word line isnot selected in the main memory. On the other hand, in the defect repairmemory, the index conversion, the row selection, the defect map reading,and the judgment of coincidence of the address and the map are executedby the usual routines. As a result, there is the disadvantage that theoutput from the defect repair memory and the comparison judgmentfollowing it are no longer in time for the access operation of the mainmemory.

In the technique of Japanese Unexamined Patent Publication (Kokai) No.11-120788, the row addresses of the data memory cells and the indexparts directly correspond, therefore when a row address is given, thedata memory cell, the defect map storage cell, and the redundant memorycell connected to same row line become accessible simultaneously.Accordingly, it is also easy to handle the above high speed access mode.

In the technique according to Japanese Unexamined Patent Publication(Kokai) No. 11-120788, however, the memory groups (sets of the defectmap storage cells and the redundant memory cells) are directly allocatedto the word lines, therefore there is the disadvantage that wastefulmemory groups not contributing to the repair of defects increase and therepair efficiency becomes low. Further, due to the restriction in chiparea, the number of the memory groups which can be allocated to eachword line by the present technique is expected to be no more than aboutone or two sets, therefore there also exists the disadvantage thatrepair becomes impossible when more than that many defective cells areincluded on the same word line.

Further, when using the technique explained above to repair defectsbefore shipping, the write operation of data of the defect map etc. forspecifying a defect location is very troublesome.

Namely, a large amount of defect locations must first be detected by afunction test using various test patterns, the data must be oncecollected and stored at the outside of the memory device under test,then it must be written into a defect map storage device correspondingto each memory device. Such a defect repair process requires enormoustime and cost. Further, when storing defect maps in the same chip, thewrite operation of the defect maps is completely different from thewrite operation of usual data. Accordingly, it becomes necessary toprovide special I/O pins for the defect maps and to perform a specialoperation mode for transferring the defect maps.

Further, in this repairing method of memory defects, there also existsthe disadvantage that defects occurring due to aging of devices etc.after shipping cannot be handled.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a semiconductor memorydevice capable of efficiently repairing defects by using limitedredundant memory while suppressing any drop in the access speedaccompanying repair of defects of the memory.

According to a first aspect of the present invention, there is provideda semiconductor memory device comprising a first memory array, a secondmemory array for storing a plurality of defective memory addresses, eachof which corresponds to each of a plurality of memory regions obtainedby dividing the first memory array for one or more word lines anddesignates a defective memory included in the corresponding memoryregion, a controlling unit for reading the defective memory address ofthe memory region including a first memory on the first memory arrayfrom the second memory array when a memory address for accessing thefirst memory is input, at least one redundant memory, and an accessswitching unit for specifying a defective memory according to thedefective memory address read out from the second memory array andswitching an access operation so that the redundant memory is accessedinstead of the specified defective memory.

Preferably, the first aspect of the present invention further comprisesa plurality of redundant memories, each of which corresponds to the eachmemory region on the first memory array and becomes accessible when amemory address for accessing a memory included in the correspondingmemory region is input, and the controlling unit executes processing forreading data from the first memory array, the second memory array, andthe redundant memory in parallel when the memory address for accessing amemory on the first memory array is input.

Preferably, the access switching unit judges whether or not an inputmemory address is an address of defective memory according to acomparison between the input memory address and a defective memoryaddress read out from the second memory array in accordance with theinput memory address, and switches an access operation so that theredundant memory is accessed instead of a defective memory when judgingthat the input memory address is an address of the defective memory.

According to a second aspect of the invention, there is provided asemiconductor memory device comprising a first memory array, a secondmemory array for storing information to specify a defective memoryincluded in each of a plurality of memory regions obtained by dividingthe first memory array, at least one redundant memory, a accessswitching unit for specifying defective memory according to theinformation stored in the second memory array and switching an accessoperation so that the redundant memory is accessed instead of thespecified defective memory, a defect detecting unit for detectingdefective memory of the first memory array by detecting errors of theread data obtained after the switching of a read operation on the accessswitching unit, and a controlling unit for updating the informationstored in the second memory array according to the detection results ofthe detecting unit.

According to a third aspect of the invention, there is provided asemiconductor memory device comprising a memory array, at least onefirst redundant memory which can replace memory on the memory array, afirst data storing unit for storing information for specifying defectivememory included in the memory array, an first access switching unit forspecifying defective memory according to the information stored in thefirst data storing unit and switching an access operation so that thefirst redundant memory is accessed instead of the specified defectivememory, a defect detecting unit for detecting the defective memoryincluded in the memory array according to a comparison between data readfrom the memory array and input data, and a controlling unit for readingdata stored in memory on the memory array in a predetermined sequencewhen a predetermined signal instructing the start of a defect detectionoperation is input and updating the information stored in the first datastoring unit according to the detection results of the defect detectingunit.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects and features of the present invention willbecome clearer from the following description of the preferredembodiments given with reference to the attached drawings, wherein:

FIG. 1 is a block diagram of an example of the configuration of asemiconductor memory device according to a first embodiment of theinvention;

FIG. 2 is a view illustrating an example of the configuration of amemory group according to the first embodiment;

FIG. 3 is a flow chart for explaining an example of the operation of thesemiconductor memory device shown in FIG. 1;

FIG. 4 is a block diagram of an example of the configuration of acomparing/judging unit and a decoder according to a second embodiment ofthe invention;

FIG. 5 is a block diagram of an example of the configuration of asemiconductor memory device according to a third embodiment of theinvention;

FIG. 6 is a view illustrating an example of the configuration of amemory group according to the third embodiment;

FIG. 7 is a block diagram of an example of the configuration of acomparing/judging unit and a decoder according to a fourth embodiment ofthe invention;

FIG. 8 is a block diagram of an example of the configuration of asemiconductor memory device according to a fifth embodiment of theinvention;

FIG. 9 is a view illustrating an example of the configuration of amemory group according to the fifth embodiment;

FIG. 10 is a flow chart for explaining an example of the operation ofthe semiconductor memory device shown in FIG. 8;

FIG. 11 is a block diagram of an example of the configuration of acomparing/judging unit and a decoder according to a sixth embodiment ofthe invention;

FIG. 12 is a block diagram of an example of the configuration of asemiconductor memory device according to a seventh embodiment of theinvention;

FIG. 13 is a view illustrating an example of the configuration of amemory group according to the seventh embodiment;

FIG. 14 is a block diagram of an example of the configuration of acomparing/judging unit and a decoder according to an eighth embodimentof the invention;

FIG. 15 is a block diagram of an example of the configuration of asemiconductor memory device according to a ninth embodiment of theinvention;

FIG. 16 is a view illustrating an example of the routine of aconventional function test; and

FIG. 17 is a view illustrating an example of the routine of the functiontest using the semiconductor memory device shown in FIG. 15.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Below, an explanation will be given of embodiments of the presentinvention with reference to the drawings.

First Embodiment

FIG. 1 is a block diagram of an example of the configuration of asemiconductor memory device according to a first embodiment of thepresent invention.

The semiconductor memory device illustrated in FIG. 1 has a first memoryarray 1 and a second memory array 2, row decoder 3 and 7, a columnselector 5, sense amplifiers 4 and 8, a comparing/judging unit 9, aselector 6, and a controlling unit 15. The first memory array 1 is anembodiment of the first memory array in the first aspect of theinvention. The second memory array 2 is an embodiment of the secondmemory array in the first aspect of the invention. The unit includingthe comparing/judging unit 9 and the selector 6 is an embodiment of theaccess switching unit in the first aspect of the invention. Thecontrolling unit 15 is an embodiment of the controlling unit in thefirst aspect of the invention.

The first memory array 1 is the main memory portion of the presentsemiconductor memory device including usually used memories. In theexample of FIG. 1, there are 16 bits of memory at each of the 2¹²×2⁸number of addresses indicated by 12 bits of row address ADR and 8 bitsof column address ADC. Accordingly, the first memory array 1 in thepresent example has a storage capacity of 2¹²×2⁸×16=16 Mbits.

The row decoder 3 selects a word line to be accessed in the first memoryarray 1 in accordance with an input 12 bits of row address ADR. The rowdecoder 7 selects the word line to be accessed in the second memoryarray 2 in accordance with 8 bits of address in the input 12 bits of rowaddress ADR.

The sense amplifier 4 reads and writes data with respect to a memorycell via each bit line of the first memory array 1. The sense amplifier8 reads and writes data with respect to a memory cell via each bit lineof the second memory array 2.

The column selector 5 selects one word's (16 bits') worth of memory fromamong one row's worth of memory of the first memory array 1 accessed viathe sense amplifier 4 in accordance with an input 8 bits of columnaddress ADC.

The second memory array 2 has a plurality of memory groups. Each memorygroup have a redundant memory for replacing defective memory existing inthe first memory array 1, a memory for storing an address (defectivememory address) for specifying defective memory, and a memory forstoring flag data indicating whether or not a defective memory addressis valid as a set.

For example, the second memory array 2 has 2⁸ number of word lines, eachof which is indicated by 8 bits of address in 12 bits of row address ADRand has the above memory group.

Accordingly, if the 8 bits of address input to the row decoder 7 areequal among two different row addresses ADR, even if the remaining 4bits are different among there, the same word line is selected for thetwo row addresses ADR at the row decoder 7. In other words, one wordline 12 in the second memory array 2 and 16 word line groups 11 in thefirst memory array 1 are in a one-to-one correspondence. When any wordline of the word line group is selected by the row decoder 3, the commonword line corresponding to this word line group is selected at the rowdecoder 7, and the memory group connected to the selected word linethereof becomes accessible.

In this way, the second memory array 2 has plurality of memory groups,each of which corresponding to each of the plurality of memory regionsobtained by dividing the first memory array 1 for each 16 word lines.

FIG. 2 is a view illustrating an example of the configuration of amemory group of the second memory array 2. For example, as shown in FIG.2, a memory group has 12 bits of memory for storing a defective memoryaddress 21, 3 bits of memory for storing flag data 24, and 1 word (16bits) of redundant memory.

A “defective memory address 21” is an address for specifying defectivememory in a memory region corresponding to a word line group 11 andincludes two addresses 22 and 23. The address 22 is the 4 bits ofaddress excluding the 8 bits of address input to the row decoder 7 in arow address ADR. The address 22 specifies one among the 16 bits of wordlines in the word line group 11. The address 23 is the 8 bits of columnaddress and specifies one word of memory on one word line.

The flag data 24 indicates whether or not the defective memory address21 of this memory group is valid. Namely, when this data flag 24 isvalid, it indicates that there is defective memory to be repaired at thedefective memory address 21, while when the data flag 24 is not valid,it indicates that there is no defective memory to be repaired at theaddress.

Further, as shown in FIG. 2, the flag data 24 is stored at the 3 bits ofmemory cells. When two or more bits among 3 bits are “1”, the flag data24 is regarded as valid in the comparing/judging unit 9 explained later.A minimum bit length for indicating valid/invalid is 1 bit. However, ifa defect occurs in the storage memory of the flag data, a fatalmalfunction is liable to be induced. Therefore, in the present example,the flag data 24 is made 3 bits and the valid/invalid judgment iscarried out by a majority decision. Due to this, the probability ofoccurrence of malfunction due to mistaken judgment of the flag data canbe suppressed.

The defective memory addresses 21 and the flag data 24 must beconstantly held irrespective of the on/off state of the power supply.For this reason, preferably the second memory array 2 is a nonvolatilememory such as a ferroelectric memory. When configuring the secondmemory array 2 by a volatile memory, for example, these data can beloaded from nonvolatile memories separately provided inside and outsidethe chip.

The comparing/judging unit 9 compares the 4 bits of address excludingthe 8 bits of address input to the row decoder 7 in a row address ADRand a addresses 22, and compares the 8 bits of column address ADC and aaddress 23, when the data stored in memory group corresponding to therow address ADR is output from sense amplifier 8.

Further, it judges whether or not 2 bits or more in the 3 bits of flagdata 24 is “1”, that is, whether or not the flag data 24 indicates thatthe defective memory addresses 21 is valid.

Then, when these addresses coincide and the flag data 24 is valid instate, the comparing/judging unit 9 judges that the input address (ADR,ADC) is an address of defective memory. Conversely, when the twoaddresses do not coincide or the flag data 24 is not valid in state, itjudges the input address (ADR, ADC) is an address of a normal memory notdefective memory.

The selector 6 selects the data of the first memory array 1 input andoutput via the column selector 5 or data 25 of redundant memory inputand output via the sense amplifier 8 in accordance with the judgmentresult of the comparing/judging unit 9. Namely, where the input addressis judged as an address of defective memory, the input/output lines ofthe sense amplifier 8 for transmitting the data 25 of redundant memoryis connected to the data bus DIO. When the input address is judged asthe address of normal memory, the input/output lines of the columnselector 5 of the first memory array 1 is connected to the data bus DIO.

The controlling unit 15 performs various controls relating to theoverall operation of the semiconductor memory device. For example, whena row address ADR and column address ADC are input and a predeterminedcontrol signal instructing writing or reading of data is input, thecontrolling unit 15 performs control for the selection of word lines inthe row decoders 3 and 7, the data read operation from the bit lines inthe sense amplifiers 4 and 8, etc. at suitable timings.

Here, an explanation will be given of the semiconductor memory deviceshown in FIG. 1 having the above configuration by referring to the flowchart shown in FIG. 3.

Steps ST10 and ST11

A row address ADR and a column address ADC are input together with apredetermined control signal instructing the writing or reading of data,whereupon, based on the control of the controlling unit 15, a selectingoperations of word lines in the row decoders 3 and 7 are executed inparallel.

Steps ST12 and ST13

The data of the memory cells connected to the word lines selected by therow decoders 3 and 7 are read out to the bit lines, amplified at thesense amplifiers 4 and 8, and latched in value. Due to this, the data ofthe memory cells on the word lines corresponding to the row address ADRare acquired from the first memory array 1, and the data of the memorygroups corresponding to the row address ADR are acquired from the secondmemory array 2.

In general, the access operation to the semiconductor memory takes thelongest time in this data sensing process. But according to thesemiconductor memory device shown in FIG. 1, the operations of the datasensing process in the first memory array 1 and the second memory array2 can be synchronized and performed in parallel without any specialconversion for the input addresses. For this reason, the delay of theaccess time accompanied with repair of defects is suppressed to thelowest limit.

Steps ST14 and ST15

The data acquired from the first memory array 1 is input to the columnselector 5, and 1 word of data in accordance with the column address ADCis selected from among the data. In parallel to this operation, amongthe data acquired from the second memory array 2, the defective memoryaddress 21 and the flag data 24 are input to the comparing/judging unit9. Then, the address 23 in the defective memory address 21 is comparedwith the column address ADC, and the address 22 is compared with part (4bits) of the row address ADR. Further, it is judged whether or not theflag data 24 is valid in state in accordance with the number of bits of“1” included in the 3 bits of the flag data 24.

Step ST16

When the defective memory addresses 22 and 23 acquired from the secondmemory array 2 and the input address coincide and the flag data 24 isvalid in state, it is judged that the input address is an address ofdefective memory. In this case, the input/output lines of the senseamplifier 8 are connected to the data bus DIO in the selector 6 so thatan access operation to the specified defective memory is switched to anaccess operation to the redundant memory 25. On the other hand, when itis judged that the input address is an address of normal memory, theinput/output lines of the column selector 5 is connected to the data busDIO at the selector 6 so that normal memory on the first memory array 1is accessed.

Step ST17

When the connection of the selector 6 has been finalized, the readingand writing with respect to the memory of the first memory array 1 orthe second memory array 2 are carried out.

As explained above, according to the semiconductor memory device shownin FIG. 1, the first memory array 1 is divided into a plurality ofmemory regions for each 16 word lines, and the defective memoryaddresses in the regions are stored in the second memory array 2. When amemory address for accessing the first memory array 1 is input, thedefective memory addresses of the memory region including the memory tobe accessed are read out from the second memory array 2.

In this way, the addresses of defective memory existing in 16 wordlines' worth of the memory regions are stored in the second memory array2. Therefore, in comparison with the case where only one word line'sworth of a memory region can be covered by one defective memory addressas disclosed in for example Japanese Unexamined Patent Publication(Kokai) No. 11-120788, addresses of broader ranges of defective memorycan be stored. For this reason, it becomes possible to repair defectsoccurring at random efficiently.

Further, the above memory regions of the first memory array 1 areregions divided for each word line. For this reason, the parts of therow addresses ADR concerned with the selection of word lines in theinput addresses can be directly used for accessing a memory group on thesecond memory array 2 and reading out data from the memory groups.Accordingly, in comparison with the case of converting or otherwiseprocessing the input address, it becomes possible to read out defectivememory addresses or other data from the second memory array 2 at a highspeed and suppress a drop in the access speed accompanied with repair ofdefects.

In addition, when an address (ADR, ADC) for accessing the first memoryarray is input, as shown in FIG. 3, the read operation to the firstmemory array 1 and the second memory array 2 are executed in parallel.

In this way, the read accesses from memory requiring the longest accesstime are carried out in parallel in two memory arrays, so the drop ofthe access speed accompanying repair of defects can be more effectivelysuppressed.

DRAMs, SRAMs, flash memories, ferroelectric memories, magnetic memories,and many other semiconductor memories have high speed access modes wherethey perform the processing up to the data sensing process (steps ST12and ST13 of FIG. 3), then repeat the following accesses while changingonly the column address by an internal counter or external control.According to the semiconductor memory device shown in FIG. 1, theselection of the memory group and data sensing in the second memoryarray 2 and the row selection and data sensing in the first memory array1 are executed in parallel, so it is possible to complete the two datasensing processes at the same timing. Namely, at the stage of repeatingthe steps after the data sensing, it is not necessary to repeat the datasensing of the memory groups, therefore, even in the high speed accessmode explained above, the repair of defects can be realized whilesuppressing a drop of the access speed.

Some large capacity memories, however, reduce the load of the bit linesand the power consumption by finely dividing the memory into a pluralityof arrays. In a semiconductor memory having such a configuration, thearray is first selected, and then the word line in the array isselected. The address used for this array selection can be regarded aspart of the row address in the present invention.

Further, in memory of a type dividing in the word line direction, wordlines of a plurality of arrays activate synchronously together in aone-to-one correspondence. The case of such a memory is essentially thesame as that of a single array in the point that the row selection isalternately carried out.

The memory of such an array division type can be applied to both of thefirst memory array 1 and the second memory array 2. The semiconductormemory device of the present embodiment operates in the same way as thatdescribed above irrespective of such an array division and can exhibitthe same effects.

Further, there is also a memory wherein a plurality of banks areprovided on the same semiconductor chip, and word lines corresponding todifferent row addresses is activated in parallel, but in the case ofsuch a memory, explained above, the repair of defects can be realizedwhile suppressing a drop of the access speed.

Some large capacity memories, however, reduce the load of the bit linesand the power consumption by finely dividing the memory into a pluralityof arrays. In a semiconductor memory having such a configuration, thearray is first selected, and then the word line in the array isselected. The address used for this array selection can be regarded aspart of the row address in the present invention.

Further, in memory of a type dividing in the word line direction, wordlines of a plurality of arrays activate synchronously together in aone-to-one correspondence. The case of such a memory is essentially thesame as that of a single array in the point that the row selection isalternately carried out.

The memory of such an array division type can be applied to both of thefirst memory array 1 and the second memory array 2. The semiconductormemory device of the present embodiment operates in the same way as thatdescribed above irrespective of such an array division and can exhibitthe same effects.

Further, there is also a memory wherein a plurality of banks areprovided on the same semiconductor chip, and word lines corresponding todifferent row addresses is activated in parallel, but in the case ofsuch a memory, the first memory array and the second memory array thesame as those explained above may be provided as a set for each bank.

Further, close linkage of two memory arrays as explained above isdesirably carried out in the same semiconductor chip capable of freelyexchanging a large number of signals with a low load. In recent years,however, there have been advances in the technique referred to SIP(system in package). It is now becoming possible to perform low load,high speed, and large volume signal exchange even in a plurality ofsemiconductor chips in a package. Accordingly, when using such atechnique, it is also possible to include two memory arrays by differentsemiconductor chips in the same package.

Second Embodiment

Next, a second embodiment of the present invention will be explained.

In the semiconductor memory device shown in FIG. 1, only one memorygroup can be utilized for the repair of defects in each memory region(memory region of 16 word line groups 11) of the first memory array 1.Contrary to this, in the semiconductor memory device according to thepresent embodiment, N (N indicates a natural number of 2 or more) numberof memory groups can be utilized for the repair of defects in one memoryregion.

The semiconductor memory device according to the present embodiment, inthe same way as the semiconductor memory device shown in FIG. 1, has afirst memory array 1, a second memory array 2, row decoders 3 and 7, acolumn selector 5, sense amplifiers 4 and 8, a selector 6, and acontrolling unit 15.

However, in the present embodiment, each word line of the second memoryarray 2 has N number of memory groups (hereinafter referred to as a“memory set”) having the configuration shown in FIG. 2. When one wordline is selected by the row decoder 7, data of one memory set (N numberof memory groups) are read out from the sense amplifier 8.

In the following explanation, these N number of memory groups arediscriminated by referring to them as the “first memory group” to the“N-th memory group”.

Further, as shown in FIG. 4, the semiconductor memory device accordingto the present embodiment has N number of comparing/judging units 9_1 to9_N and an OR circuit 94 for computing the logical OR of the judgmentsignals explained later output from these comparing/judging units.

Each comparing/judging unit 9_i (i indicates an integer of 1 to N) has acomparator 90_i, a flag judger 91_i, an AND circuit 92_i, and a passgate 93_i.

Each comparator 90_i receives as input 4 bits address in the row addressADR and the column address ADC (hereinafter, this two addresses will bereferred to as the “address AD1”) and compares the address AD1 and adefective memory address 21_i read out from the i-th memory group. Whenthe two coincide, it outputs the signal of “1”, while when the two donot coincide, it outputs the signal of “0”.

Each flag judger 91_i receives as input the 3 bits of flag data 24_iread out from the i-th memory group. When two or more bits of “1” areincluded in these 3 bits, it outputs the signal of “1”, while when theyare not included, it outputs the signal of “0”.

Each AND circuit 92_i computes the logical AND of output signals of thecomparator 90_i and the flag judger 91_i and outputs this computationresult as the judgment signal indicating whether or not the inputaddress (ADR, ADC) is an address of defective memory. Namely, when thisjudgment signal is “1”, the input address is the address of defectivememory, while when the judgment signal is “0”, the input address is theaddress of normal memory.

Accordingly, the output signal of the OR circuit 94, which is thelogical OR of all judgment signals of the AND circuits 92_1 to 92_N,becomes “1” when the input address is an address of defective memory,while becomes “0” when it is an address of normal memory. The outputsignal of the OR circuit 94 is output to a judgment signal line L1.

Each pass gate 93_i is connected to the input/output lines of the senseamplifier 8 having one terminal connected to the redundant memory of thei-th memory group and having the other terminal connected to theselector 6 via a common lines L2. Then, these two terminals becomeconductive when the judgment signal of the AND circuit 92_i is “1” andshut when the judgment signal is “0”.

The selector 6 connects the common lines L2 connected to the pass gates93_1 to 93_N and the data bus DIO when the output signal of the ORcircuit 94 output to the judgment signal line L1 is “1”. When the outputsignal is “0”, the selector 6 connects input/output lines L3 of thecolumn selector 5 and the data bus DIO.

Next, an explanation will be given of the operation of the semiconductormemory device according to the present embodiment having the aboveconfiguration.

The overall operation of the semiconductor memory device according tothe present embodiment is the same as the flow chart shown in FIG. 3.The difference from the semiconductor memory device shown in FIG. 1resides in the point that the defect judgment operation in step ST15 andthe access switch operation in step ST16 are carried out based on thedata of N number of memory groups.

Namely, the address AD1 constituted by part of the input address (ADR,ADC) is compared with N number of defective memory addresses output fromthe N number of memory groups. Then, when the address AD1 coincides withfor example the defective memory address 21_i and the flag data 24_icorresponding to this is valid in state, the judgment signal of the ANDcircuit 92_i becomes “1”, the pass gate 93_i becomes conductive, and theoutput signal of the OR circuit 94 becomes “1”.

Here, when assuming that all defective memory addresses stored in Nnumber of memory groups are different addresses, only the output signalof the AND circuit 92_i becomes “1” among the judgment signals of theAND circuits 92_1 to 92_N, and only the pass gate 93_i becomesconductive among the pass gates 93_1 to 93_N.

Accordingly, among the N number of redundant memories on the word linesselected by the row decoder 7, only the redundant memory included in thesame memory group as the memory from which the valid defective memoryaddress coinciding with the address AD1 was read out becomes able to beaccessed from the data bus DIO.

As explained above, in the semiconductor memory device according to thepresent embodiment, the second memory array 2 is provided with aplurality of memory sets, each of which corresponding to each of aplurality of memory regions (memory regions of the word line group 11)on the first memory array 1 and has N number of memory groups. When theaddress (ADR, ADC) for accessing the first memory array 1 is input, thememory set corresponding to the memory region including the memory to beaccessed are selected, and the defective memory addresses and the flagdata are read out from the selected memory set. Further, at this time,each redundant memory included in the selected memory set becomesaccessible. The comparing/judging units 9_1 to 9_N compare the defectivememory addresses 21_1 to 21_N read out from the selected memory set andthe addresses AD1, and judge whether or not the flag data 24_1 to 24_Nread out from the memory groups are valid. When any of thecomparing/judging units 9_1 to 9_N judges that the input address is anaddress of defective memory based on the results of this addresscomparison and flag judgment, an access operation to the defectivememory is switched to an access operation to redundant memory includedin the same memory group from which the address of the defective memorywas read out.

Accordingly, it becomes possible to repair a plurality of defectivememories in one memory region of the first memory array 1.

Third Embodiment

Next, a third embodiment of the present invention will be explained.

In the semiconductor memory devices according to the first and secondembodiments, when there is even 1 bit of a memory cell having a defectincluded in 1 word (16 bits) of memory, all memory cells of the 1 wordare replaced by 1 word of the redundant memory. On the other hand, inthe semiconductor memory device shown in FIG. 5 explained next, thememory cell having the defect in the 1 word is further designated by theaddress stored in the memory group, and this defective memory cell isreplaced by 1 bit of a redundant memory cell.

FIG. 5 is a block diagram of an example of the configuration of thesemiconductor memory device according to the third embodiment of thepresent invention. The same notations as those of FIG. 1 indicate thesame components.

Namely, the semiconductor memory device illustrated in FIG. 5, in thesame way as the semiconductor memory device shown in FIG. 1, has a firstmemory array 1, row decoders 3 and 7, a sense amplifier 4, a columnselector 5, a comparing/judging unit 9, and a controlling unit 15.Further, as components different from those of the semiconductor memorydevice shown in FIG. 1, it has a second memory array 2A, a senseamplifier 8A, a selector 6A, and a decoder 10.

The second memory array 2A has a different configuration of the memorygroups in comparison with the first memory array 1. FIG. 6 is a viewillustrating an example of the configuration of a memory group of thesecond memory array 2A. For example, as shown in FIG. 6, a memory groupof the second memory array 2A has memory for the defective memoryaddress 21 and the flag data 24 in the same way as already explainedFIG. 2 and, differently from it, has 4 bits of memory for storing thedefective cell address 26 and 1 bit of redundant memory.

The defective cell address 26 designates a defective memory cell amongthe 16 memory cells which configure a memory designated by the defectivememory address 21. Accordingly, the 1 bit of a defective memory celldesignated by the defective cell address 26 in the 1 word designated bythe defective memory address 21 is replaced by 1 bit of the redundantmemory in a memory group.

The sense amplifier 8A reads and writes the data with respect to thememory groups shown in FIG. 6. In comparison with the sense amplifier 8,the number of bits of the input/output data is different.

The selector 6A connects one input/output line of the sense amplifier 8Aconnected to 1 bit of redundant memory to the corresponding bit of thedata bus DIO in place of any indicated one of the 16 bits of theinput/output lines of the column selector 5 in response to a decodesignal supplied from the decoder 10, and connects the remaining 15 bitsof the input/output lines to the corresponding bits of the data bus DIO.Alternatively, it connects all of the 16 bits of the input/output linesof the column selector 5 to the corresponding bits of the data bus DIO.

When the comparing/judging unit 9 judges that the input address is anaddress of defective memory, the decoder 10 generates a decode signalfor switching any one of the 16 bits of the input/output lines of thecolumn selector 5 to a redundant memory use input/output line based onthe 4 bits of defective cell address 26 output from the memory group.When it judges that the input address is an address of normal memory,the decoder 10 generates a decode signal for connecting all of the 16bits of input/output lines to the data bus DIO.

The overall operation of the semiconductor memory device shown in FIG. 5having the above configuration is the same as that in the alreadyexplained flow chart shown in FIG. 3. The difference from thesemiconductor memory device shown in FIG. 1 resides in the point that anaccess operation to the 1 bit of the defective memory cell designated bythe defective cell address 26 in the 1 word of the defective memorydesignated by the defective memory address 21 is switched to an accessoperation to 1 bit of the redundant memory in the access switchoperation of step ST16.

In the case of defects occurring for memory cells at random, even in theway of replacing 1 bit, a defect can be repaired with a probability notdifferent from the way of replacing 16 bits. In addition, the bit lengthof the memory group can be shortened, therefore the circuit scale of thesecond memory array and the sense amplifier can be reduced.

Fourth Embodiment

Next, a fourth embodiment of the present invention will be explained.

In the semiconductor memory device shown in FIG. 5, only one memorygroup can be utilized for repair of defects in each memory region of thefirst memory array 1. Contrary to this, in the semiconductor memorydevice according to the present embodiment, N number of memory groupscan be utilized for the repair of defects with respect to one memoryregion.

The semiconductor memory device according to the present embodiment, inthe same way as the semiconductor memory device shown in FIG. 5, has afirst memory array 1, a second memory array 2A, row decoders 3 and 7, acolumn selector 5, sense amplifiers 4 and 8A, a selector 6A, and acontrolling unit 15.

However, in the present embodiment, each word line of the second memoryarray 2A has N number of memory groups having the configuration shown inFIG. 6. When one word line is selected by the row decoder 7, the data ofN number of memory groups (the first memory group to the N-th memorygroup) is read out from the sense amplifier 8A.

Further, as shown in FIG. 7, the semiconductor memory device accordingto the present embodiment has N number of comparing/judging units 9A_1to 9A_N and an OR circuit 94 for computing the logical OR of thejudgment signals output from these comparing/judging units.

Each comparing/judging unit 9A_i, in the same way as thecomparing/judging unit 9_i shown in FIG. 4, has a comparator 90_i, aflag judger 91_i, and an AND circuit 92_i. Further, as componentsdifferent from those of the comparing/judging units 9_i, it has passgates 95_i and 96_i.

Each pass gate 95_i has one terminal connected to the input/output linesfor transmitting the defective cell address 26_i of the i-th memorygroup therethrough and has the other terminal connected to the inputterminal of the defective cell address of the decoder 10 via a commonlines L4. Then, these two terminals become conductive when the judgmentsignal of the AND circuit 92_i is “1” and shut when the judgment signalis “0”.

Each pass gate 96_i has one terminal connected to the input/output linesof the sense amplifier 8 connected to the 1 bit of redundant memory ofthe i-th memory group and has the other terminal connected to theselector 6A via a common lines L5. Then, these two terminals becomeconductive when the judgment signal of the AND circuit 92_i is “11” andshut when the judgment signal is “0”.

The selector 6A has selectors 6_0 to 6_15 corresponding to 16 bits asshown in for example FIG. 7. A selector 6_k (k indicates an integer of 0to 15) selects the common line L5 connected to the pass gates 96_1 to96_N or the k-th bit signal line of the input/output lines L6 of thecolumn selector 5 in response to the decode signal supplied for theselector 6_k by the decoder 10, and connects the selected line to thek-th bit signal line of the data bus DIO.

Next, an explanation will be given of the operation of the semiconductormemory device according to the present embodiment having the aboveconfiguration.

The overall operation of the semiconductor memory device according tothe present embodiment is the same as that of the semiconductor memorydevice shown in FIG. 5. The difference from this resides in the pointthat the defect judgment operation and the access switch operation arecarried out based on the data of N number of memory groups.

Namely, the address AD1 constituted by part of the input address (ADR,ADC) is compared with N number of defective memory addresses output fromN number of memory groups. When the address AD1 coincides with forexample 21_i and, at the same time, the flag data 24_i corresponding tothis is valid in state, the judgment signal of the AND circuit 92_ibecomes “1”, the pass gates 95_i and 96_i become conductive, and theoutput signal of the OR circuit 94 becomes “1”.

Here, if all of the defective memory addresses stored in the N number ofmemory groups are different, among the pass gates 95_1 to 95_N, only thepass gate 95_i becomes conductive, and among the pass gates 96_1 to96_N, only the pass gate 96_i becomes conductive.

In this case, the defective cell address 26_i of the i-th memory groupis input to the decoder 10, and the data input/output line of theredundant memory of the i-th memory group is connected to the commonline L5 connected to the selectors 6_0 to 6_15. Then, when a decodesignal in accordance with the defective cell address 26_i is generatedin the decoder 10 and the selection states of the selectors 6_0 to 6_15are set, the signal line of any bit of the data bus DIO is connected tothe data input/output line of the redundant memory of the i-th memorygroup, and the signal lines of the other bits are connected to theinput/output lines of corresponding bits of the column selector 5.

As explained above, according to the semiconductor memory device of thepresent embodiment, when an input address is judged to be an address ofa defective memory, an access operation to a memory cell designated by adefective cell address in a defective memory is switched to an accessoperation to a redundant memory. In this access switching operation, theredundant memory being accessed instead of the defective memory cell isincluded in the same memory group which includes the memory outputtingvalid defective memory address coinciding with the address AD1.

Accordingly, it becomes possible to repair a plurality of defectivememories in one memory region of the first memory array 1, and furtherpossible to repair each 1 bit defect. Therefore, the bit length of thememory groups becomes shorter, and the circuit scale of the secondmemory array and the sense amplifier thereof can be reduced.

Fifth Embodiment

Next, a fifth embodiment of the present invention will be explained.

In the semiconductor memory devices shown in FIG. 1 and FIG. 5,redundant memory was provided in the second memory array different fromthe usually used first memory array. For this reason, it is difficult toaccess the redundant memory at the same timing as that for the memory inthe first memory array.

For example, when setting redundant memory to the accessible stateaccording to the defective memory addresses read out from the memorygroups, then writing in the redundant memory, the load and resistance ofthe signal path driven when writing are completely different between theredundant memory on the second memory array and the memory on the firstmemory array, therefore there is possibility that the write speeds ofthe two will different. If the write speed to the second memory array isslower than the write speed to the first memory array, the write speedto redundant cells will restrict the access speed of the entire memory.

Such a problem also restricts the configuration of the second memoryarray. For example, when the first memory array is a DRAM, it becomesimpossible to utilize a ferroelectric memory, flash memory, etc. as thesecond memory array because their write speed is slower than that of thesecond memory array.

In the semiconductor memory device shown in FIG. 8 explained next, byproviding redundant cells on the same memory array, the difference ofthe access speed described above between the usually used memory and theredundant memory is eliminated.

FIG. 8 is a block diagram of an example of the configuration of asemiconductor memory device according to the fifth embodiment of thepresent invention.

The semiconductor memory device illustrated in FIG. 8 has a first memoryarray 1B, a second memory array 2B, row decoders 3 and 7, a columnselector 5B, sense amplifiers 4B and 8B, a selector 6B, thecomparing/judging unit 9, a decoder 10, and a controlling unit 15.

The same notations as those of FIG. 1, FIG. 5, and FIG. 8 indicate thesame components. Namely, the row decoders 3 and 7, the comparing/judgingunit 9, the decoder 10, and the controlling unit 15 are the same asthose already explained by referring to FIG. 1 and FIG. 5. Accordingly,their explanations will be omitted below. Only the other components willbe explained.

The first memory array 1B is the main memory portion in the presentsemiconductor memory device and has 16 bits of memory and 1 bit ofredundant memory at (2¹²)×(2⁸) addresses each indicated by 12 bits ofrow address ADR and 8 bits of column address ADC. That is, it has 1 bitof redundant memory for each 1 word of memory indicated by an inputaddress.

Accordingly, the first memory array 1B in the present example has astorage capacity of (2¹²)×(2⁸)×17=17 Mbits. The storage capacity islarger than the first memory array 1 by exactly the 1 Mbit of theredundant memory.

The sense amplifier 4B reads and writes data with respect to the memorycells via bit lines of the first memory array 1B.

The sense amplifier 8B reads and writes data with respect to the memorycells via bit lines of the second memory array 2B.

The sense amplifiers 4B and BB have different numbers of bits of inputand output data in comparison with the above sense amplifiers 4 and 8.

The column selector 5B selects 17 bits of memory (set of the usuallyused 1 word of memory+1 bit of redundant memory) in accordance with the8 bits of input column address ADC from one row's worth of memory of thefirst memory array 1B accessed via the sense amplifier 4B.

The second memory array 2B has a plurality of memory groups. Each memorygroup includes a memory for storing a defective memory address in eachof a plurality of memory regions obtained by dividing the first memoryarray 1B for each 16 word lines, a memory for storing flag dataindicating whether or not the defective memory address is valid, and amemory for storing a defective cell address designating a defectivememory cell among a plurality of memory cells which configure a memorydesignated by the defective memory address.

The second memory array 2B has for example 2⁸ number of word linesdesignated by 8 bits of address in the 12 bits of a row address ADR.Each word line has an above memory group.

Accordingly, one word line 12 in the second memory array 2B and 16 wordline groups 11 in the first memory array 1B are in a one-to-onecorrespondence. When any word line of a word line group in the firstmemory array 1B is selected at the row decoder 3, the common word linecorresponding to this word line group is selected at the row decoder 7,whereby the memory group connected to the selected word line thereofbecomes accessible.

Namely, the second memory array 2B has a plurality of memory groups,each of which corresponds to each memory region obtained by dividing thefirst memory array 1B for each 16 word lines.

FIG. 9 is a view illustrating an example of the configuration of amemory group of the second memory array 2B.

For example, as shown in FIG. 9, a memory group of the second memoryarray 2B has 12 bits of memory for storing a defective memory address21, 3 bits of memory for storing flag data 24, and 4 bits of memory forstoring a defective cell address 26. This configuration is equal to thatof the memory group shown in FIG. 6 minus the 1 bit of redundant memory.

The defective memory address 21, the flag data 24, and the defectivecell address 26 must always be held irrespective of the on/off state ofthe power supply. For this reason, preferably the second memory array 2Bis a nonvolatile memory such as a ferroelectric memory. When configuringthe second memory array 2B by a volatile memory, for example the datacan be loaded from nonvolatile memories separately provided inside oroutside the memory chip as well.

The selector 6B connects 1 bit of the input/output line of the columnselector 5 connected to 1 bit of the redundant memory to thecorresponding bit of the data bus DIO in place of any indicated bit ofthe 16 bits of the input/output lines of the column selector 5 connectedto the usually used 16 bits of memory in response to the decode signalsupplied from the decoder 10, and connects the remaining 15 bits of theinput/output lines to the corresponding bits of the data bus DIO.Alternatively, it connects all of the 16 bits of the input/output linesof the column selector 5 connected to the usually used 16 bits of memoryto the corresponding bits of the data buses DIO.

Here, an explanation will be given of the operation of the semiconductormemory device shown in FIG. 8 having the above configuration byreferring to the flow chart shown in FIG. 10.

Steps ST20 and ST21

A predetermined control signal indicating the writing or reading of thedata is input, whereby the selection operations of word lines at the rowdecoders 3 and 7 are executed in parallel under the control of thecontrolling unit 15.

Steps ST22 and ST23

The data of the memory cells connected to the word lines selected by therow decoders 3 and 7 are read out to the bit lines, amplified by thesense amplifiers 4B and 8B, and latched in values. By this, the data ofmemory cells on the word lines corresponding to the row address ADR areacquired from the first memory array 1B, and the data of the memorygroup corresponding to the row address ADR are acquired from the secondmemory array 2B.

In usual access to the semiconductor memory, the longest time isrequired for this data sensing process, but according to thesemiconductor memory device shown in FIG. 8, the operations of the datasensing process in the first memory array 1B and the second memory array2B can be synchronized and performed in parallel without performingspecial conversion for the input addresses. For this reason, the delayof the access time accompanying the repair of defects can be suppressedto the lowest limit.

Steps ST24 and ST25

The data acquired from the first memory array 1B is input to the columnselector 5B, and 17 bits data (1 word+1 redundant bit) in accordancewith the column address ADC is selected from among the acquired data.

On the other hand, among the data acquired from the second memory array2B, the defective memory addresses 21 and the flag data 24 are input tothe comparing/judging unit 9. Then, the addresses 23 of the defectivememory are compared with the column address ADC, and the addresses 22are compared with part (4 bits) of the row address ADR. Further, it isjudged whether or not the flag data 24 is valid in state in accordancewith the number of bits of “1” included in the 3 bits of flag data 24.

Step ST26

When a coincidence between the defective memory addresses 21 acquiredfrom the second memory array 2B and the input address is found and theflag data 24 is valid in state, it is judged that the input address isan addresses of defective memory. In this case, based on the defectivecell addresses 26 output from the memory group, one of the 16 bits ofthe input/output lines of the column selector 5B connected to theusually used memories is switched to 1 bit of the input/output line ofthe column selector 5B connected to the redundant memory.

On the other hand, when it is judged that the input address is theaddress of normal memory, all of the 16 bits of the input/output linesconnected to the usually used memory are connected to the data bus DIO.

Step ST27

When the connection of the selector 6B is finalized, the reading andwriting operation with respect to the usually used memory or theredundant memory of the first memory array 1B are carried out.

As explained above, according to the semiconductor memory device shownin FIG. 8, redundant memory is included in the first memory array 1B.When one memory in the first memory array 1B is selected for accessingin accordance with the input address (ADR, ADC), the redundant memoryconnected to the same word line of the selected memory becomesaccessible. Then, when it is judged that the input address is an addressof a defective memory in the comparing/judging unit 9, an accessoperation to the defective memory cell designated by the defective celladdress 26 in the defective memory is switched to an access operation to1 bit of redundant memory connected to the same word line of thedefective memory cell.

In this way, by providing usually used memory and redundant memory onthe same memory array, the difference of the access speed between thesetwo memories becomes very small, so the problem of a drop of the accessspeed when the destination of access is switched to redundant memory canbe solved. Further, since such a problem is solved, the restriction ofthe type of the memory used in the first memory array 1B and the secondmemory array 2B can be eliminated.

Other than this, the feature that a wide range of defective memoryaddresses is stored in the memory groups, the feature that access to thememory groups is carried out without adding any special conversionprocessing to the input address, the feature that the read operationwith respect to two memory arrays 1B and 2B are executed in parallel,and the feature that access to 1 bit of a defective memory cell in 1word of memory is switched to access to redundant memory cell are thesame as the already explained semiconductor memory devices shown in FIG.1 and FIG. 5, so it is possible to exhibit the same effects to those.

Further, the feature that memories of the array division type and thebank type can be applied to the first memory array 1B and the secondmemory array 2B is the same as the already explained semiconductormemory devices.

Sixth Embodiment

Next, a sixth embodiment of the present invention will be explained.

In the semiconductor memory device shown in FIG. 8, only one memorygroup can be utilized for the repair of defects in each memory region ofthe first memory array 1B. Contrary to this, in the semiconductor memorydevice according to the present embodiment, N number of memory groupscan be utilized for the repair of defects with respect to one memoryregion.

The semiconductor memory device according to the present embodiment, inthe same way as the semiconductor memory device shown in FIG. 8, has afirst memory array 1B, a second memory array 2B, row decoders 3 and 7, acolumn selector 5B, sense amplifiers 4B and 8B, a selector 6B, a decoder10, and a controlling unit 15.

Further, as shown in FIG. 11, the semiconductor memory device accordingto the present embodiment has N number of comparing/judging units 9B_1to 9B_N and an OR circuit 94 for computing the logical OR of thejudgment signals output from these comparing/judging units.

Each comparing/judging unit 9B_i, in the same way as thecomparing/judging unit 9A_i shown in FIG. 7, has a comparator 90_i, aflag judger 91_i, an AND circuit 92_i, and a pass gate 95_i. Thedifference from the comparing/judging unit 9A_i resides in the pointthat the pass gate 96_i is not included.

Each pass gate 95_i has one terminal connected to the input/output linesfor transmitting the defective cell address 26_i of the i-th memorygroup therethrough and has the other terminal connected to the defectivecell address input terminal of the decoder 10 via the common lines L4.These two terminals become conductive when the judgment signal of theAND circuit 92_i is “1” while shut when the judgment signal is “0”.

The selector 6B, in the same way as the selector 6A shown in FIG. 7, hasselectors 6_0 to 6_15 corresponding to the 16 bits. The difference fromthe selector 6A resides in the connection of the redundant memory side.Namely, as shown in FIG. 11, in the selector 6B, an input/output line L7for the redundant memory of the column selector 5B is connected toterminals of the selectors 6_0 to 6_15 on the redundant memory side.

The operation of the semiconductor memory device according to thepresent embodiment having the above configuration is almost the same asthat of the semiconductor memory device explained in the fourthembodiment except that the redundant memory to be accessed is in thesecond memory array 2B.

Namely, when it is judged that the input address is the address of adefective memory, an access operation to the a memory cell designated bya defective cell address in a defective memory is switched to an accessoperation to a redundant memory included in the first memory array 1B.In this access switching operation, the redundant memory being accessedinstead of the defective memory cell forms a pair with the memorydesignated by the input address.

Accordingly, it becomes possible to repair a plurality of defectivememories in one memory region of the first memory array 1B, theprobability of repair can be raised even in memory having many smalldefects, and the yield can be improved.

Seventh Embodiment

Next, a seventh embodiment of the present invention will be explained.

In the semiconductor memory devices of FIG. 1, FIG. 5, and FIG. 8explained above, when the word line is selected in the first memoryarray and the column is selected, the usually used memory and theredundant memory are switched by the selector. Further, in this way, theaccess switching operation is carried out after the usual data selectionstage. However, the present invention is not restricted to such aconfiguration. Many variations can exist.

In the semiconductor memory device shown in FIG. 12 explained next, thecolumn selection operation is carried out in two stages before and afterthe selector for access switching between usually used memory andredundant memory.

FIG. 12 is a block diagram of an example of the configuration of asemiconductor memory device according to the seventh embodiment of thepresent invention.

The semiconductor memory device illustrated in FIG. 12 has a firstmemory array 1C, a second memory array 2C, row decoders 3 and 7, columnselectors 5C and 13, sense amplifiers 4C and 8C, a selector 6C, acomparing/judging unit 9C, a decoder 10C, and a controlling unit 15.

Here, the same notations as those of FIG. 1 and FIG. 12 indicate thesame components. Namely, the row decoders 3 and 7 and the controllingunit 15 are the same as those already explained by referring to FIG. 1.Accordingly, in the following explanation, their explanation will beomitted, and an explanation will be given of the other components.

The first memory array 1C is the main memory portion in the presentsemiconductor memory device and has 1 word (16 bits) of memory at 2¹²×2⁸addresses each indicated by 12 bits of row address ADR and 8 bits ofcolumn address ADC. Further, when defining 4 continuous words of memoryregion as a sub-memory region, 2 bits of redundant memory are providedfor each sub-memory region. Namely, the memory region corresponding to16 word lines are further divided into sub-memory regions for each 4words. Two bits of redundant memory are provided for each sub-memoryregion.

Accordingly, in the first memory array 1C, the storage capacity ofusually used memory is 16 Mbits or the same as that of the first memoryarray 1, and the storage capacity of redundant memory is 2¹²×2⁶×2=512Kbits.

The sense amplifier 4C reads and writes the data with respect to thememory cells via bit lines of the first memory array 1C. The senseamplifier 8C reads and writes the data with respect to the memory cellsvia bit lines of the second memory array 2C. The sense amplifiers 4C and8C have different numbers of bits of input/output data in comparisonwith the above sense amplifiers 4 and 8.

The column selector 5C selects 66 bits of memory (4 words of usuallyused memory+2 bits of redundant memory) from among 1 row's worth ofmemory of the first memory array 1C accessed via the sense amplifier 4Cin accordance with the part (6 bits) of the column address ADC.

The second memory array 2C has a plurality of memory groups. Each memorygroup includes memories for storing a sub-memory region address, a flagdata, a defective cell address and a redundant memory designation data.The sub-memory region address designates a sub-memory region (4 word)including a defective memory in a memory regions (16 word lines). Theflag data indicates whether or not the sub-memory region address isvalid. The defective cell address designates a defective memory cellamong a plurality of memory cells which configure the sub-memory regiondesignated by the sub-memory region address. The redundant memorydesignation data designates a redundant memory to replace a defectivememory cell designated by the defective cell address.

The second memory array 2C has for example 28 word lines indicated by 8bits of addresses among 12 bits of row addresses ADR, and has the abovememory group on each of the word lines.

Accordingly, one word line 12 in the second memory array 2C and 16 wordline groups 11 in the first memory array 1C are in a one-to-onecorrespondence. When any word line of a word line group in the firstmemory array 1C is selected at the row decoder 3, the common word linecorresponding to this word line group is selected at the row decoder 7,whereby the memory group connected to the selected word line thereofbecomes accessible.

Namely, the second memory array 2C has a plurality of memory groups,each of which corresponds to each of a plurality of memory regionsobtained by dividing the first memory array 1C for each 16 word lines.

FIG. 13 is a view illustrating an example of the configuration of amemory group of the second memory array 2C.

For example, as shown in FIG. 13, a memory group of the second memoryarray 2C has 10 bits of memory for storing an address 21C of thesub-memory region including a defective memory (hereinafter, describedas the defective sub-memory region), 3 bits of memory for storing theflag data 24, 6 bits of memory for storing the defective cell address26C in the sub-memory region, and 1 bit of memory for storing theredundant memory designation data 27.

The address 21C of a sub-memory region is an address for specifying thedefective sub-memory region in the memory region corresponding to theabove word line group 11 and includes two addresses 22 and 23. Theaddress 22 is the 4 bits of address excluding the 8 bits of addressinput to the row decoder 7 in the row address ADR as already explained.By this, one of the 16 word lines in the word line group 11 isspecified. The address 23C is 6 bits of address in the 8 bits of thecolumn address and specifies a 4-word sub-memory region in the memoryregion.

The defective cell address 26C is an address for specifying 1 bit of adefective memory cell in a 4-word (64-bit) defective sub-memory region.

The redundant memory designation data 27 is data for indicating which of2 bits of redundant memory provided for each sub-memory region is to beused for replacing a defective memory cell.

The comparing/judging unit 9C compares the 4 bits of address excludingthe 8 bits of address input to the row decoder 7 in the row address ADRand the addresses 22 included in a data of memory group when the secondmemory array outputs the data of memory group via the sense amplifier 8Call together in accordance with the row address ADR. Further, itcompares 6 bits of address in the 8 bits of column address ADC and theaddress 23C of the sub-memory region. Further, it also judges whether ornot 2 bits or more in 3 bits of the flag data 24 become “1”, that is,whether or not the flag data 24 is valid in state.

Then, when the two addresses coincide and the flag data 24 is valid instate, the comparing/judging unit 9C judges that the input address (ADR,ADC) is the address of a defective sub-memory region. Conversely, wherethe two addresses do not coincide or the flag data 24 is not valid instate, the comparing/judging unit 9C judges that the input address (ADR,ADC) is not the address of a defective sub-memory region.

When the comparing/judging unit 9C judges that the input address is theaddress of a defective sub-memory region, the decoder 10C generates adecode signal so as to switch any one bit of the input/output lines (64bits) for the usually used memory of the column selector 5C to theinput/output line for the redundant memory designated by the redundantcell designation data 27 based on the 6 bits of defective cell address26C output from the memory groups. When it judges that the input addressis the address of normal memory, it generates the decode signal so thatall of the input/output lines for the usually used memory are connectedto signal lines D64.

The selector 6C connects the input/output line of the column selector 5Cconnected to the redundant memory designated by the redundant memorydesignation data 27 to the one of 64 bits of signal lines D64 in placeof indicated 1 bit of input/output line among the 64 bits ofinput/output lines of the column selector 5 connected to the 64 bits ofusually used sub-memory regions in accordance with the decode signalsupplied from the decoder 10C, and connects the remaining 63 bits of theinput/output lines to the corresponding bits of the signal lines D64.Alternatively, it connects all of the 64 bits of the input/output linesof the column selector 5 to the corresponding bits of the signal linesD64.

The column selector 13 selects 16 bits of the signal lines from the 64bits of signal lines D64 connected to the selector 6C in accordance withthe remaining 2 bits of address excluding the 6 bits of the columnaddress ADC input to the comparing/judging unit 9C, and connects theselected signal lines to the data bus DIO.

Next, an explanation will be given of the operation of the semiconductormemory device shown in FIG. 12 having the above configuration.

When a predetermined control signal instructing the writing or readingoperation of the data is input, the selection operations of the wordlines in the row decoders 3 and 7 are carried out in parallel under thecontrol of the controlling unit 15. By this, one row's worth of thememory of the first memory array 1C becomes accessible via the senseamplifier 4C, and the memory group (FIG. 13) of the second memory array2C corresponding to the accessible memory also becomes accessible viathe sense amplifier 8C.

The column selector 5C selects 66 bits of memory (4 words of sub-memoryregion+2 bits of redundant memory) from among 1 row's worth of memory ofthe first memory array 1C which became accessible in accordance with 6bits of address in the column address ADC.

While, among the memory group which became accessible in the secondmemory array 2C, the addresses 21C of the sub-memory regions and theflag data 24 are input to the comparing/judging unit 9C. Then, theaddress 23C included in the address 21C is compared with part (6 bits)of the column address ADC, and the address 22 is compared with part (4bits) of the row address ADR. Further, it is judged whether or not theflag data 24 is valid in state in accordance with the number of the bitsof “1” included in these 3 bits of flag data 24.

When a coincidence between defective memory address 21C acquired fromthe second memory array 2C and the input address coincide is found andthe flag data 24 is valid in state, it is judged that the input addressis the addresses of a defective sub-memory region. In this case, anaccess operation to memory designated by the defective cell address 26Cin the defective sub-memory region is switched to an access operation toredundant memory designated by the redundant memory designation data 27.Namely, the selector 6C switches the input/output line of the columnselector 5C connected to the defective cell in the usually used memoryto the input/output line of the column selector 5C connected toredundant memory, and connects the switched line to the correspondingbit of the signal line D64. On the other hand, when it is judged thatthe input address is not the address of a defective sub-memory region,all of the input/output lines of the column selector 5 connected tousually used memory are connected to the signal lines D64.

Then, the column selector 13 selects 16 bits of signal lines from amongthe 64 bits of signal lines D64 connected to the selector 6C based onthe remaining part (2 bits) of the column address ADC and connects theselected lines to the data bus DIO.

When the connections of the selector 6C and the column selector 13 arefinalized, the reading and writing operation with respect to the usuallyused memory or the redundant memory of the first memory array 1C arecarried out.

As explained above, in the semiconductor memory device shown in FIG. 12,each of the memory regions obtained by dividing the first memory array1C for each 16 word lines is further divided into sub-memory regions foreach 4 words. 2 bits of redundant memory are provided for eachsub-memory region. When an address for accessing the first memory array1C is input, the memory of one sub-memory region becomes accessible inaccordance with the input address and, at the same time, the redundantmemory corresponding to this sub-memory region becomes accessible.Further, the comparing/judging unit 9C judges whether or not the inputaddress is the address of a defective sub-memory region based on thedata of the memory group read out from the second memory array 2C. Whenit is judged to be the address of a defective sub-memory region, theconnection of the selector 6C is set so that an access operation to thedefective memory in the sub-memory region is switched to an accessoperation to the redundant memory corresponding to the sub-memoryregion.

In this way, defects of memory included in a 4-word sub-memory regioncan be repaired together, therefore, even when a series of memoryincluded in a sub-memory region is sequentially accessed, it becomesunnecessary to repair the defects for every access, so the access speedcan be raised.

In the high-speed access mode of the semiconductor memory, there is amode designating for example the column address, then continuouslyreading data from 2 to 4 words of memory continuing from this columnaddress (burst mode). As in the present example, if a wide range ofdefects can be repaired together in advance, such a high-speed mode canbe handled without delay.

Eighth Embodiment

Next, an eighth embodiment of the present invention will be explained.

In the semiconductor memory device shown in FIG. 12, only one memorygroup can be utilized for the repair of defects in a memory region ofthe first memory array 1C. Contrary to this, in the semiconductor memorydevice according to the present embodiment, N number of memory groupscan be utilized for the repair of defects for one memory region.

In the same way as the semiconductor memory device shown in FIG. 12, thesemiconductor memory device according to the present embodiment has afirst memory array 1C, a second memory array 2C, row decoders 3 and 7,column selectors 5C and 13, sense amplifiers 4C and 8C, a selector 6C,and a controlling unit 15.

In the present embodiment, each word line of the second memory array 2Chas N number of memory groups having the configuration shown in FIG. 13.When the row decoder 7 selects one word line, the data of N number ofmemory groups (the first memory group to the N-th memory group) is readout from the sense amplifier 8C.

Further, as shown in FIG. 14, the semiconductor memory device accordingto the present embodiment has N number of comparing/judging units 9C_1to 9C_N, OR circuits 94_1 and 94_2 for computing the logical OR of twosystems of judgment signals output from these comparing/judging units,and two systems of decoders 10C_1 and 10C_2.

Each comparing/judging unit 9C_i has a comparator 90C_i, a flag judger91_i, AND circuits 92_i, 98_i, and 99_i, and a pass gate 97_i.

Each comparator 90C_i receives as input 4 bits of address of the rowaddress ADR and 6 bits of address of the column address ADC (hereinafterthese two addresses will be described as the address AD2) and comparesthe input address AD2 and the defective sub-memory region address 21C_iread out from the i-th memory group. When the two addresses coincide, itoutputs the signal of “1”, while when they do not coincide, it outputsthe signal of “0”.

Each flag judger 91_i and AND circuit 92_i have functions the same asthose of the already explained comparator 90_i. Namely, the flag judger91_i outputs “1” when the flag data 24_i of the i-th memory group isvalid in state, while outputs “0” when it is not valid in state. EachAND circuit 92_i outputs the logical AND of the comparator 90C_i and theflag judger 91_i as the judgment signal. When this judgment signal is“1”, the input address is the address of a defective sub-memory region,while when the judgment signal is “0”, the input address is the addressof a normal sub-memory region.

Each pass gate 97_i has three terminals (the first terminal to the thirdterminal) and switches the connection configuration of them inaccordance with the judgment signal of the AND circuit 92_i. The firstterminal is connected to the input/output lines of the defective celladdress 26C_i of the i-th memory group. The second terminal is connectedto the defective cell address input terminal of the decoder 10C_1 via acommon lines L9. The third terminal is connected to the defective celladdress input terminal of the decoder 10C_2 via a common lines L11. Whenthe judgment signal of the AND circuit 92_i is “1”, the first terminaland the second terminal become conductive and the first terminal and thethird terminal are shut. When the judgment signal is “0”, the firstterminal and the third terminal become conductive and the first terminaland the second terminal are shut.

Each AND circuit 98_i outputs the logical AND of the judgment signal ofthe AND circuit 92_i and the redundant memory designation data 27_i readout from the i-th memory group as the first judgment signal. Each ANDcircuit 99_i outputs the logical AND of the judgment signal of the ANDcircuit 92_i and the signal obtained by inverting the logic of theredundant memory designation data 27_i as the second judgment signal.Accordingly, when the redundant memory designation data 27_i is “1”, thefirst judgment signal becomes equal to the judgment signal of the ANDcircuit 92_i and the second judgment signal becomes “0”. When theredundant memory designation data 27_i is “0”, the second judgmentsignal becomes equal to the judgment signal of the AND circuit 92_i andthe first judgment signal becomes “0”.

The OR circuit 94_1 outputs the logical OR of the first judgment signalsoutput from the comparing/judging units 9C_1 to 9C_N to the firstjudgment signal line L8. The OR circuit 94_2 outputs the logical OR ofthe second judgment signals output from the comparing/judging units 9C_1to 9C_N to the second judgment signal line L10.

The selector 6C has 64 selectors 6C_0 to 6C_63 corresponding to the 64bits of input/output lines L14 of the column selector 5C connected tothe usually used memory.

Each selector 6C_n (n indicates an integer from 0 to 63) selects one ofan input/output line L12 of the column selector 5C connected to thefirst redundant memory, an input/output line L13 of the column selector5C connected to the second redundant memory, or the n-th bit signal lineof input/output lines L14 of the column selector 5C connected to theusually used memory in response to the decode signal supplied for theselector 6C_n from the decoders 10C_1 and 10C_2, and connects theselected line to the n-th bit signal line of the signal lines D64.

The decoder 10C_1 receives as input the signal of the first judgmentsignal line L8 and the defective cell addresses output from the secondterminals of the pass gates 97_1 to 97_N via the common lines L9 andsets the connection states of the selectors 6C_1 to 6C_N in accordancewith this. Namely, when the signal of the first judgment signal line L8is “1”, the decode signal is generated so that any bit of the signallines D64 is connected to the input/output line L12 for the firstredundant memory in accordance with the defective cell address input viathe common lines L9 and the remaining bits of the signal lines D64 areconnected to corresponding bits of input/output lines L14 of the usuallyused memory (some remaining bits of the signal lines D64 are connectedto input/output lines L13 for the second redundant memory depending onthe decoding result of the decoder 10C_2).

Further, when the signal of the first judgment signal line L8 is “0”, itgenerates a decode signal so that all bits of the signal lines D64 areconnected to corresponding bits of the input/output lines L14 of theusually used memory (some bits of the signal lines D64 are connected tothe input/output lines L13 for the second redundant memory depending onthe decoding result of the decoder 10C_2).

The decoder 10C_2 receives as input the signal of the second judgmentsignal line L10 and defective cell addresses output from the thirdterminals of the pass gates 97_1 to 97_N via the common lines L11 andsets the connection states of the selectors 6C_1 to 6C_N in accordancewith this. Namely, when the signal of the second judgment signal lineL10 is “1”, it generates the decode signal so that any bit of the signallines D64 is connected to the input/output line L13 of the secondredundant memory in accordance with the defective cell address input viathe common lines L11 and the remaining bits of the signal lines D64 areconnected to the corresponding bits of the input/output lines L14 forthe usually used memory (some remaining bits of the signal lines D64 areconnected to the input/output lines L12 for the first redundant memorydepending on the decoding result of the decoder 10C_1).

Further, when the signal of the second judgment signal line L10 is “0”,it generates the decode signal so that all bits of the signal lines D64are connected to corresponding bits of the input/output lines L14 of theusually used memory (some bits of the signal lines D64 are connected tothe input/output lines L12 for the first redundant memory according tothe decoding result of the decoder 10C_1).

Next, an explanation will be given of the operation of the semiconductormemory device according to the present embodiment having the aboveconfiguration. When the memory address (ADR, ADC) is input together witha control signal instructing writing/reading, the selection operationsof the word lines of the row decoders 3 and 7 are executed in parallel,and 1 row's worth of memory of the first memory array 1C and N number ofmemory groups of the second memory array 2C corresponding to them becomeaccessible via the sense amplifiers.

The column selector 5C selects 66 bits of memory (4 words of sub-memoryregion+2 bits of redundant memory) in accordance with the 6 bits ofaddress in the column address ADC from among 1 row's worth of memory ofthe accessible first memory array 1C. The comparing/judging units 9C_1to 9C_N compare the sub-memory region addresses 21C_1 to 21C_N read outfrom the memory groups and the input address AD2, judge the flag data24_1 to 24_N read out from the memory groups, and judge whether or notthe input address is an address of a defective sub-memory region basedon the results.

The judgment results of the comparing/judging units 9C_1 to 9C_N aredistributed to either of two systems in accordance with the values ofredundant memory designation data 27_1 to 27_N, that is, which of tworedundant memories (the first redundant memory or the second redundantmemory) is to be used for repairing the defective memory cells.

For example, when redundant memory designation data 27_i input to thecomparing/judging unit 9C_i is set at “1”, the first redundant memory isused for the repair of the defective memory cell based on the judgmentresult. In this case, the judgment signal of an AND circuit 92_i isinput to the decoder 10C_1 from the AND circuit 98_i via the OR circuit94_1 and the common line L8. Further, a defective cell address 26C_i isinput to the decoder 10C_1 via the second terminal of the pass gate 97_iand the common line L9. In this case, when the judgment signal of theAND circuit 92_i is “1”, one among 64 bits of signal lines D64designated by the defective cell address 26C_i is connected to theinput/output line L12 of the first redundant memory via one of theselectors 6C_1 to 6C_63.

Conversely, when redundant memory designation data 27_i input to thecomparing/judging unit 9C_i is set at “0”, the second redundant memoryis used for the repair of the defective memory cell based on thejudgment result. In this case, the judgment signal of the AND circuit92_i is input to the decoder 10C_2 from the AND circuit 99_i via the ORcircuit 94_2 and the common line L10. Further, the defective celladdress 26C_i is input to the decoder 10C_2 via the third terminal ofthe pass gate 97_i and the common lines L9. Then, in this case, when thejudgment signal of the AND circuit 92_i is “11”, one among 64 bits ofsignal lines D64 designated by the defective cell address 26C_i isconnected to the input/output line L13 of the second redundant memoryvia one of the selectors 6C_1 to 6C_63.

The column selector 13 selects 16 bits of signal lines from theselection result of the selector 6C based on 2 bits of address andconnects this to the data bus DIO. When the connections of the selector6C and the column selector 13 are finalized, the reading and writingoperation with respect to the usually used memory or the redundantmemory of the first memory array 1C are carried out.

As explained above, according to the semiconductor memory device of thepresent embodiment, it is possible to obtain the same effects as thoseof the semiconductor memory device shown in FIG. 12, and further itbecomes possible to repair a plurality of defective memories in onememory region of the first memory array 1C. Accordingly, the probabilityof repair can be raised even in a memory having many small defects, andthe yield can be improved.

Ninth Embodiment

Next, a ninth embodiment of the present invention will be explained.

In the semiconductor memory device according to the present embodiment,defective memory of the first memory array is detected, and informationfor specifying the defective memory stored in the second memory array isupdated in accordance with this detection result.

FIG. 15 is a block diagram of an example of the configuration of asemiconductor memory device according to the ninth embodiment of thepresent invention. The semiconductor memory device shown in FIG. 15 hasa first memory array 40, a second memory array 41, an address register42, a register 43, an access switching unit 44, a defect detecting unit45, and a controlling unit 46. The first memory array 40 is anembodiment of the first memory array in the second aspect of theinvention. The second memory array 41 is an embodiment of the secondmemory array in the second aspect of the invention. The defect detectingunit 45 is an embodiment of the defect detecting unit in the secondaspect of the invention. The controlling unit 46 is an embodiment of thecontrolling unit in the second aspect of the invention.

The first memory array 40 is the main memory portion of the presentsemiconductor memory device including the usually used memory.

The second memory array 41 stores information for specifying defectivememory in each of four memory regions (R1 to R4) obtained by dividingthe first memory array. In the example of FIG. 15, it has memory regionsM1 to M4 for storing defective memory specifying information concerningthe memory regions R1 to R4. Note that the first memory array is dividedinto a plurality of memory regions using part of the row addresses etc.as in for example the above embodiments.

The address register 42 holds the address of the memory to be accessedwhen the first memory array 40 is accessed.

The register 43 holds one memory region (M1 to M4) worth of defectivememory specifying information read out from the second memory array 41.When a latch type sense amplifier is used in the second memory array 41,it can be used as the register 43 too.

The access switching unit 44 specifies the defective memory based on thedefective memory specifying information held in the register 43 andswitches access operation so that not illustrated redundant memory isaccessed instead of the specified defective memory. Namely, defectivememory is not selected and redundant memory is selected to repair anydefect. This defective memory repair routine is realized by for examplethe same method as the above embodiments.

The defect detecting unit 45 detects error included in the data read outafter the access switching operation of the access switching unit 44based on the comparison with for example input data for detecting error.When error is detected, the information etc. concerning the position ofany memory cell where error was detected is output to the controllingunit 46.

The controlling unit 46 performs various control and processingconcerning the entire operation such as control concerning the readingand writing of the data with respect to the first memory array 40 andthe second memory array 41, and the processing for updating theinformation of the second memory array 41 based on the detection resultof the defect detecting unit 45.

Next, an explanation will be given of the operation of the semiconductormemory device shown in FIG. 15 having the above configuration.

When the first memory array 40 is accessed according to an address heldin the address register 42, the controlling unit 46 reads out ainformation for specifying defective memory from the memory region (M1to M4) on the second memory array 41 corresponding to the memory region(R1 to R4) including the memory to be accessed, and holds the readinformation in the register 43. For example, when 1 word of data is readout from the memory 47 of the region R2 on the first memory array 40,the information for specifying defective memory in the region R2 is readout from the memory region M2 on the second memory array 41 and holds itin the register 43.

When the defect detecting unit 45 detects a defect of the memory andreceives the position information etc. of a memory cell, the controllingunit 46 acquires the address of the defective memory from the addressregister 42 and newly generates a information for specifying defectivememory in the memory region R2 based on the acquired address and theposition information from the defect detecting unit 45. Then, thecontrolling unit 46 updates the information held in the register 43based on this generated information. For example, when the flag data ofeach memory group stored in the register 43 is checked and there is amemory group where the flag data is invalid in state (unused), thecontrolling unit 46 writes the information for specifying defectivememory into the register corresponding to the memory group and, at thesame time, changes the invalid state of the flag data to the valid state(use). When the register 43 is updated, the controlling unit 46 writesback all data after the update into corresponding memory region of thesecond memory array 41.

As explained above, according to the semiconductor memory device shownin FIG. 15, defective memory of the first memory array 40 is detected inaccordance with the error of the data read out after the accessswitching operation, and the information for specifying defective memorystored in the second memory array 41 is updated based on this detectionresult. In this way, it is possible to automatically detect anydefective memory inside the memory device and update the information forspecifying defective memory capable of repairing the detected defectivememory, therefore it becomes possible to easily repair a new defectivememory occurring due to for example aging of the device after shippingthe product.

It is also possible to detect error of the data in the defect detectingunit 45 by attaching an error detecting code such as parity data to thedata of the first memory array 40 and utilize this. When detecting errorand updating the defective memory specifying information explained abovewhenever for example data is read out, it becomes possible toautomatically repair a memory defect occurring after shipping due toaging etc. without burdening the user.

For example, when the data read out in the first memory array 40 iscomprised of (64+7) bits and 7 bits are used as the parity, the defectdetecting unit 45 can detect and correct 1 bit of error. If furtherdefect of the memory occurs in the state where 1 bit of error has beencorrected, this defect cannot be repaired by the conventional method ofcorrecting error with only parity. On the other hand, when automaticallyrepairing a detected error part by replacement with a redundant memoryas described above, even if a defect occurs again, the error can becorrected by the parity again, therefore the defect can be repaired. Inthis case, defects can be repeatedly repaired so far as there is spacein the redundant memory and the memory for storing the information forspecifying defective memory.

Further, the above function of automatically repairing defective memoryspecifying information is very useful particularly when repairing alarge amount of small defects. For example, it is possible to generatethe information for specifying defective by utilizing the presentfunction before the shipping. By this, the time and the cost taken fordetecting and repairing defects can be greatly reduced.

The conventional simplest routine for defect detection and repair is theapplication of the routine used in the write verification etc. in theflash memory and is as follows:

(1) A input data is first stored in a register at the time of writingthe input data to a memory array.

(2) After the input data is written into the memory array, then the samelocation is immediately read out.

(3) The input data and the output data are compared, and error isdetected.

(4) Any defect is additionally repaired based on the detected error.

However, it is difficult to detect defects efficiently and sufficientlyby the above technique. For example, small defects occur along withholding data. In order to detect this, a constant standing period isnecessary after holding, but with this method, it becomes necessary tolet data stand whenever 1 word is written, so an enormous test timebecomes necessary. Further, there are also memory defects that causeerroneous writing into adjacent cells at the time of writing. Suchdefects cannot be detected by the method of checking memory cells one byone. In addition, a variety of tests become necessary in accordance withvarious cases of defects, but it is difficult to cope with such testsflexibly by the above technique.

If using the test technique of using the semiconductor memory deviceshown in FIG. 15 to detect defective memory and automatically generatethe information for specifying it to deal with such problems of theprior art, it is possible to flexibly cope with all test sequences.

FIG. 16 is a view illustrating an example of the routine of aconventional function test, while FIG. 17 is a view illustrating anexample of the routine of a function test using the semiconductor memorydevice shown in FIG. 15.

In the conventional function test shown in FIG. 16, the preparation of awrite pattern at the time of writing, the preparation of a test pattern(correct) equal to the write pattern at the time of reading, and thecomparison the data read out from the semiconductor memory device withthe test pattern are carried out at the tester side.

On the other hand, in the function test shown in FIG. 17, in place ofthe conventional read operation, the test pattern is supplied from thetester side to the semiconductor memory device. In the semiconductormemory device, any defect is detected by the comparison between the testpattern supplied from the tester and the data read out from the memoryarray, and the information for specifying defective memory stored in thesemiconductor memory device is updated in accordance with the comparisonresult.

Namely, when a predetermined signal instructing the start of a defectdetection operation is input from the tester, the controlling unit 46reads out the data stored in memory of the first memory array 40 in apredetermined sequence. At this time, data found to be “correct” issequentially input to the memory device from the tester. The defectdetecting unit 45 sequentially compares the data read out from the firstmemory array 40 and the test pattern from the tester and detectsdefective memory included in the first memory array 40 based on thiscomparison result. When the defect detecting unit 45 detects defectivememory, the information for specifying the detected defective memory iswritten into the second memory 41 by the controlling unit 46.

In this way, the troublesome process performed outside of thesemiconductor memory device for detecting and repairing defects issimplified, so the time and the cost required for the process can bereduced. Further, the complex processing on the tester side isunnecessary, therefore it is possible to apply this to the conventionalfunction test as it is.

Note that the test mode for detecting defects and updating theinformation for specifying defective memory inside the semiconductormemory device in this way must be distinguished from the normaloperation mode. Therefore it is possible to for example provide a testpin in the semiconductor memory device and supply an appropriate signalto the test pin to execute the test mode. It is also possible to input asignal from the conventional input pins by a special combination so asto execute the text mode.

Further, it is also possible to provide a means for notifying theexistence of error or whether or not the information for specifyingdefective memory was updated through a specific output pin etc. of thesemiconductor memory device from the memory side to the tester side.

Further, the above repair of defects is preferably performed aftermanually repairing any large defects. The repair unit for repairinglarge defects is for example unit of bit line or word line. By this, theautomatic defect repair technique explained above is applied for thisrepair, and the consumption of large amount of memories used forrepairing small defects can be prevented.

For the repair of such large defect, it is possible to apply the repairtechnique using fuses etc. as the means for storing the defect map foreach bit line or word line.

Namely, the semiconductor memory device shown in FIG. 15 can be furtherprovided with a second redundant memory having equivalent memory size tothat of memories connected to one or more bit lines or one or more wordlines on the first memory array 41, a data storing unit for storinginformation to specify the bit line or word line connected to defectivememory on the first memory array 41, a second access switching unit forspecifying the bit line or word line connected to defective memory basedon the information stored in the data storing unit and switching anaccess operation so that the second redundant memory is accessed insteadof memories connected to the specified bit line or word line.

After storing the information of the bit line and word line in whichlarge defects occurs in this data storing unit in advance, by applyingthe above automatic defect repair technique, it is possible to avoid theproblem of consuming a large amount memories used for repairing smalldefects.

Further, the automatic defect repair technique is not limited to theconfiguration of the semiconductor memory device shown in FIG. 15.Namely, it can also be applied to various semiconductor memory deviceshaving a memory array, at least one redundant memory which can replacememory on this memory array, a data storing means for storinginformation for specifying defective memory included in the memoryarray, and an access switching means for specifying defective memorybased on the information stored in the data storing means and switchingan access operation so that the redundant memory is accessed instead ofthe specified defective memory.

While some embodiments of the present invention were explained above,the present invention is not limited to these embodiments. Variousmodifications are possible.

For example, in the above embodiments, the example was shown wherein theredundant memory was included in one of the first memory array or thesecond memory array, but the present invention is not limited to this.It is also possible to provide the redundant memories in for example athird memory array independent from these memory arrays. Each redundantmemory may corresponds to each of memory regions which are obtained bydividing the first memory array for one or more word lines, and maybecomes accessible when a memory address for accessing a memory includedin the corresponding memory region is input.

In the semiconductor memory device according to the fifth and sixthembodiments, the first memory array 1B has only one redundant memory foreach word of memory accessed by an input address, but may have aplurality of redundant memories too. The semiconductor memory device inthis case has substantially the same configuration as the semiconductormemory device shown in FIG. 12 or FIG. 14 minus the column selector 13except for the point that the bit lengths of signals are different.

Namely, in this case, each memory group includes memory for storing theredundant memory designation data. The controlling unit 15 reads out theredundant memory designation data when the memory address is input. Thecomparing/judging unit and the selector switch an access operation sothat redundant memory designated by the redundant memory designationdata is accessed instead of a memory cell designated by the defectivecell address when it is judged that the input address is the address ofdefective memory.

Summarizing the effects of the invention, defects can be repairedefficiently by using the limited redundant memory while suppressing anydrop of the access speed accompanying repair of defects of the memory.

1. A semiconductor memory device comprising: a first memory array; asecond memory array for storing a plurality of defective memoryaddresses, each of which corresponds to each of a plurality of memoryregions obtained by dividing said first memory array for one or moreword lines and designates a defective memory included in thecorresponding memory region; a controlling unit for reading thedefective memory address of the memory region including a first memoryon said first memory array from said second memory array when a memoryaddress for accessing the first memory is input; at least one redundantmemory; and an access switching unit for specifying a defective memoryaccording to the defective memory address read out from said secondmemory array and switching an access operation so that said redundantmemory is accessed instead of the specified defective memory.
 2. Asemiconductor memory device as set forth in claim 1, comprising aplurality of redundant memories each of which corresponds to the eachmemory region on said first memory array and becomes accessible when amemory address for accessing a memory included in the correspondingmemory region is input, and wherein said controlling unit executesprocessing for reading data from said first memory array, said secondmemory array, and said redundant memory in parallel when the memoryaddress for accessing a memory on said first memory array is input.
 3. Asemiconductor memory device as set forth in claim 2, wherein said accessswitching unit judges whether or not an input memory address is anaddress of defective memory according to a comparison between the inputmemory address and a defective memory address read out from said secondmemory array in accordance with the input memory address, and switchesan access operation so that the redundant memory is accessed instead ofa defective memory when judging that the input memory address is anaddress of the defective memory.
 4. A semiconductor memory device as setforth in claim 3, wherein: said redundant memory is included in saidsecond memory array; said second memory array includes a plurality ofmemory sets, each of which corresponds to the memory region on saidfirst memory array and has a predetermined number of memory groups; saideach memory group has a memory for storing the defective memory addressand a redundant memory; said controlling unit reads defective memoryaddresses from said memory set corresponding to the memory regionincluding a first memory on said first memory array, and sets theredundant memories included in the same memory set being accessible,when a memory address for accessing the first memory is input; and saidaccess switching unit judges whether or not an input memory address isan address of defective memory according to a comparison between theinput memory address and defective memory addresses read out from saidmemory set in accordance with the input memory address, and switches anaccess operation so that the redundant memory included in the samememory group outputting an address of a defective memory is accessedinstead of the defective memory when judging that the input memoryaddress is the address of the defective memory.
 5. A semiconductormemory device as set forth in claim 4, wherein: said memory group has amemory for storing a defective cell address for designating a defectivememory cell among a plurality of memory cells which configure a memorydesignated by the defective memory address; said controlling unit readsthe defective cell addresses from said memory set corresponding to thememory region including a first memory on said first memory array when amemory address for accessing the first memory is input; and said accessswitching unit switches an access operation so that the redundant memoryis accessed instead of a memory cell designated by the defective celladdress in a defective memory when judging that the input memory addressis the address of the defective memory.
 6. A semiconductor memory deviceas set forth in claim 3, wherein: said redundant memory is included inthe first memory array; a redundant memory connected to the same wordline of a first memory on said first memory array becomes accessiblewhen the first memory becomes accessible in accordance with the inputmemory address; said second memory array can stores one or moredefective memories for each memory region on said first memory array;and said access switching unit judges whether or not the input memoryaddress is an address of defective memory according to a comparisonbetween the input memory address and one or more defective memoryaddresses read out from said second memory array in accordance with theinput memory address, and switches an access operation so that theredundant memory connected to the same word line of a defective memoryis accessed instead of the defective memory when judging that the inputmemory address is an address of the defective memory.
 7. A semiconductormemory device as set forth in claim 6, wherein: said first memory arrayhas a plurality of redundant memories, each of which corresponds to amemory designated by the input memory address; said second memory arrayincludes a plurality of memory sets, each of which corresponds to eachmemory region of said first memory array and has one or more memorygroups; said memory group has a memory for storing the defective memoryaddress and a memory for storing a defective cell address fordesignating a defective memory cell among a plurality of memory cellswhich configure a memory designated by the defective memory address;said controlling unit reads the defective memory address and thedefective cell address from said memory set corresponding to the memoryregion including a first memory on said first memory array when a memoryaddress for accessing the first memory is input; and said accessswitching unit switches an access operation so that the redundant memorycorresponding to a defective memory is accessed instead of a memory celldesignated by the defective cell address in a defective memory whenjudging that the input memory address is an address of the defectivememory.
 8. A semiconductor memory device as set forth in claim 7,wherein: said first memory array includes a plurality of redundantmemory sets, each of which corresponds to each memory on said firstmemory array capable of being designated by the input memory address andhas a plurality of redundant memories; said memory group has a memoryfor storing a redundant memory designation data designating theredundant memory to replace a memory cell designated by the defectivecell address; said controlling unit reads the redundant memorydesignation data from said memory set corresponding to the memory regionincluding a first memory on said first memory array when a memoryaddress for accessing the first memory is input; and said accessswitching unit switches an access operation so that the redundant memorydesignated by the redundant memory designation data is accessed insteadof a memory cell designated by the defective cell address in a defectivememory when judging that the input memory address is the address of thedefective memory.
 9. A semiconductor memory device as set forth in claim3, wherein: said each redundant memory corresponds to each of aplurality of sub-memory regions obtained by further dividing the memoryregion on said first memory array; a redundant memory corresponding tothe sub-memory region including a first memory becomes accessible whenthe first memory becomes accessible in accordance with the input memoryaddress; and said access switching unit switches an access operation sothat the redundant memory corresponding to a sub-memory region includinga defective memory is accessed instead of the defective memory whenjudging that the input memory address is an address of the sub-memoryregion including the defective memory.
 10. A semiconductor memory deviceas set forth in claim 9, comprising a plurality of redundant memorysets, each of which corresponds to each sub-memory region on said firstmemory array and has a plurality of redundant memories, and wherein: aredundant memory set corresponding to a sub-memory region including afirst memory on said first memory array becomes accessible when thefirst memory becomes accessible in accordance with the input memoryaddress; said second memory array includes a plurality of memory sets,each of which corresponds to each memory region on said first memoryarray and has one or more memory groups; said memory group has a memoryfor storing a sub-memory region address designating a sub-memory regionincluding a defective memory, a memory for storing a defective celladdress for designating a defective memory cell among a plurality ofmemory cells which configure a sub-memory region designated by thesub-memory region address, and a memory for storing a redundant memorydesignation data designating the redundant memory to replace a memorycell designated by the defective cell address; said controlling unitreads the sub-memory region addresses, the defective cell addresses andthe redundant memory designation data from said memory set correspondingto the memory region including a first memory on said first memory arraywhen a memory address for accessing the first memory is input; and saidaccess switching unit judges whether or not the input memory address isan address of sub-memory region including a defective memory accordingto a comparison between the input memory address and one or moresub-memory region addresses read out from said memory set in accordancewith the input memory address, and switches an access operation so thatthe redundant memory designated by the redundant memory designation datais accessed instead of a memory cell designated by the defective celladdress in a defective memory when judging that the input memory addressis an address of a sub-memory region including the defective memory. 11.A semiconductor memory device as set forth in claim 3, wherein: saidsecond memory array includes a plurality of memory groups, each of whichcorresponds to the memory region on said first memory array; said eachmemory group has a memory for storing the defective memory address and amemory for storing a flag data indicating whether or not the storeddefective memory address is valid; said controlling unit reads thedefective cell address and the flag data from said memory groupcorresponding to the memory region including a first memory on saidfirst memory array when a memory address for accessing the first memoryis input; and said access switching unit judges whether or not the inputmemory address is a defective memory according to a state of the flagdata read out from said memory group as well as said comparison
 12. Asemiconductor memory device as set forth in claim 11, wherein: said eachmemory group has a plurality of memories for storing the flag data; andsaid access switching unit regards a defective memory address as validin case where a number of memories storing the valid flag data exceeds apredetermined number in the memory group.
 13. A semiconductor memorydevice comprising: a first memory array; a second memory array forstoring information to specify a defective memory included in each of aplurality of memory regions obtained by dividing said first memoryarray; at least one redundant memory; a access switching unit forspecifying defective memory according to the information stored in saidsecond memory array and switching an access operation so that theredundant memory is accessed instead of the specified defective memory;a defect detecting unit for detecting defective memory of said firstmemory array by detecting errors of the read data obtained after theswitching of a read operation on said access switching unit; and acontrolling unit for updating the information stored in said secondmemory array according to the detection results of said detecting unit.14. A semiconductor memory device as set forth in claim 13, wherein saiddefect detecting unit detects defective memory according to apredetermined error detecting code included in the read data obtainedafter the switching of a read operation on said fist memory.
 15. Asemiconductor memory device as set forth in claim 13, wherein saiddefect detecting unit detects defective memory according to a comparisonbetween a given data for error detection and the read data obtainedafter the switching of a read operation on said fist memory.
 16. Asemiconductor memory device comprising: a memory array; at least onefirst redundant memory which can replace memory on the memory array; afirst data storing unit for storing information for specifying defectivememory included in said memory array; an first access switching unit forspecifying defective memory according to the information stored in saidfirst data storing unit and switching an access operation so that thefirst redundant memory is accessed instead of the specified defectivememory; a defect detecting unit for detecting the defective memoryincluded in the memory array according to a comparison between data readfrom the memory array and input data; and a controlling unit for readingdata stored in memory on said memory array in a predetermined sequencewhen a predetermined signal instructing the start of a defect detectionoperation is input and updating the information stored in the first datastoring unit according to the detection results of the defect detectingunit.
 17. A semiconductor memory device as set forth in claim 16,comprising: a second redundant memory having equivalent memory size tothat of memories connected to one or more bit lines or one or more wordlines on said memory array; a second data storing unit for storinginformation to specify the bit line or word line connected to defectivememory on said memory array; and a second access switching unit forspecifying the bit line or word line connected to defective memory basedon the information stored in said second data storing unit and switchingan access operation so that said second redundant memory is accessedinstead of memories connected to the specified bit line or word line.